1. Field of the Invention
The present invention relates to electrostatic discharge and electrical overstress protection devices and methods of fabricating same. More particularly, the present invention relates to protection devices having charge dissipating structures within the electrostatic discharge and electrical overstress protection devices.
2. State of the Art
Electrostatic discharge (hereinafter xe2x80x9cESDxe2x80x9d) and electrical overstress (hereinafter xe2x80x9cEOSxe2x80x9d) are two common phenomenon that occur during human or mechanical handling of semiconductor integrated circuitry (hereinafter xe2x80x9cICxe2x80x9d) devices. The input pins to an IC device are highly sensitive to damage from the voltage spike of an ESD, which can reach potentials in excess of hundreds of volts. If a charge of this magnitude is brought into contact with a pin of an IC device, a large flow of current may surge through the IC device. Although this current surge may be of limited energy and duration, it can cause a breakdown of insulating barriers within the IC device (usually gate oxide insulating barriers of an MOS (metal-oxide-semiconductor) IC device). This breakdown of the insulating barriers within an IC device can result in permanent damage to the IC device and, once damaged, it is impossible to repair the IC device.
All pins of a MOS IC device must be provided with protective circuits to prevent such ESD voltages from damaging the insulating barriers (e.g., gate oxide) therein. The most common ESD protection schemes presently used in MOS IC devices rely on the parasitic bipolar transistors associated with an nMOS (n-channel or negative channel metal-oxide-semiconductor) device. These protective circuits are normally placed between the input and output pads (i.e., pin locations) on a semiconductor chip (which contains the IC device) and the transistor gates to which the input and output pads are electrically connected. With such protective circuits under stress conditions, the dominant current conduction path between the protected pin and ground involves the parasitic bipolar transistor of that nMOS device. This parasitic bipolar transistor operates in the snapback region under pin positive with respect to ground stress events. The dominant failure mechanism found in the NMOS protection device operating in snapback conditions is the onset of second breakdown. Second breakdown is a phenomena that induces thermal runaway in the IC device wherever the reduction of the ESD current is offset by the thermal generation of carriers. Second breakdown is initiated in an IC device under stress, known as electrical overstress or EOS, as a result of self-heating. The peak nMOS device temperature at which second breakdown is initiated is known to increase with the stress current level. The time required for the structure to heat-up to this critical temperature is dependent on the device layout and stress power distributed across the device.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of IC devices are ongoing goals of the computer industry. The advantage of increased miniaturization of components include: reduced-bulk electronic equipment, improved reliability by reducing the number of solder or plug connections, lower assembly and packaging costs, and improved circuit performance. In pursuit of increased miniaturization, IC devices have been continually redesigned to achieve ever higher degrees of integration, which has reduced the size of the IC device. However, as the dimensions of the IC devices are reduced, the geometry of the circuit elements have also decreased. In MOS IC devices, the gate oxide thickness has decreased to below 10 nanometers (nm), and breakdown voltages are often less than 10 volts. With decreasing geometries of the circuit elements, the failure susceptibility of IC devices to ESD and EOS increases, and, consequently, providing adequate levels of ESD/EOS protection, has become increasingly more difficult.
An exemplary method of fabricating an ESD/EOS protection structure (i.e., transistor) is illustrated in FIGS. 29-38. FIG. 29 illustrates a first intermediate structure 200 in the production of a transistor. This first intermediate structure 200 comprises a semiconductor substrate 202, such as a lightly doped P-type silicon substrate, which has been oxidized to form thick field oxide areas 204 and exposed to an implantation processes to form an n-type source region 206 and an n-type drain region 208. A transistor gate member 212 is formed on the surface of the semiconductor substrate 202 residing on a substrate active area 214 spanned between the source region 206 and the drain region 208. The transistor gate member 212 comprises a lower buffer layer 216 separating a gate conducting layer 218 of the transistor gate member 212 from the semiconductor substrate 202. Transistor insulating spacer members 222 are formed on either side of the transistor gate member 212. A cap insulator 224 is formed on the top of the transistor gate member 212. An insulative barrier layer 226 is disposed over the semiconductor substrate 202, the thick field oxide areas 204, the source region 206, the drain region 208, and the transistor gate member 212.
As shown in FIG. 30, an etch mask 232 is patterned on the surface of the insulative barrier layer 226, such that openings 234 in the etch mask 232 are located substantially over the source region 206 and the drain region 208. The insulative barrier layer 226 is then etched through openings 234 to form vias 236 which expose at least a portion of the source region 206 and the drain region 208, as shown in FIG. 31. The etch mask 232 is then removed, as shown in FIG. 32. A first conductive material 238 is deposited over the insulative barrier layer 226 to fill the vias 236, as shown in FIG. 33. The first conductive material 238 is planarized, as shown in FIG. 34, to electrically separate the first conductive material 238 within each via 236 (see FIG. 33), thereby forming contacts 242. The planarization is usually performed using a mechanical abrasion process, such as chemical mechanical planarization (CMP).
A deposition mask 244 is patterned on the insulative barrier layer 226, having openings 246 over the contacts 242, as shown in FIG. 35. A second conductive material 248 is deposited over the deposition mask 244 to fill the deposition mask openings 246, as shown in FIG. 36. The second conductive material 248 is planarized, as shown in FIG. 37, to electrically separate the second conductive material 248 within each deposition mask opening 246 (see FIG. 35). The planarization is usually performed using a mechanical abrasion, such as a CMP process. The deposition mask 244 is then removed to leave the second conductive material forming a source contact metallization 252 and a drain contact metallization 254, as shown in FIG. 38.
Although methods as described above are used in the industry, it is becoming more difficult to control the proper alignment of the etch mask 232 for the formation of the contacts 242, as tolerances become more and more stringent. For example, as shown in FIGS. 39 and 40, misalignment of the etch mask 232 can occur. Thus, as shown in FIG. 40, when the insulative barrier layer 226 is etched through the misaligned etch mask 232 to form a first via 256 and a second via 258, the etch forming the first via 256 can destroy a portion of the transistor insulating spacer member 222 and/or the cap insulator 224 to expose the gate conducting layer 218 of the transistor gate member 212. Thus, when a conductive material (not shown) is deposited in the first via 256, the gate conducting layer 218 will short, rendering the transistor ineffectual. Furthermore, the misaligned etch mask 232 can also result in the second via 258 exposing a portion of the thick field oxide area 204. However, since the etch to form the second via 258 is generally an oxide insulator-type etch, the etch may also etch through the thick field oxide area 204 to form a third via 262, thereby exposing a portion of the semiconductor substrate 202. Thus, when a conductive material (not shown) is deposited in the second via 258, the conductive material may short with the exposed portion of the semiconductor substrate 202.
Therefore, it would be desirable to design a transistor which can be fabricated with less sensitivity to misalignment and which has a more efficient charge dissipating structure to handle electrostatic discharge and electrical overstress.
The present invention relates to methods of forming electrostatic discharge and electrical overstress protection devices for integrated circuits and devices so formed. The protection devices comprise at least one transistor which includes a shared electrical contact within source regions and within drain regions for more efficient dissipation of an electrostatic discharge which, in turn, reduces the incidence of electrical overstress. The protection devices further include contact plugs and contact landing pads which render the fabrication of such devices less sensitive to alignment constraint in the formation of contacts for the protection device.
An exemplary method of fabrication of the transistor of the present application comprises forming an intermediate structure, including a semiconductor substrate, such as a lightly doped P-type silicon substrate, which has been oxidized to form thick field oxide areas and exposed to n-type implantation processes to form a source region and a drain region. A transistor gate member is formed on the surface of the semiconductor substrate residing on a substrate active area spanned between the source region and the drain region. The transistor gate member comprises a lower buffer layer separating the gate conducting layer of the transistor gate member from the semiconductor substrate. Transistor insulating spacer members, preferably silicon dioxide, are formed on either side of the transistor gate member and a cap insulator is formed on the top of the transistor gate member.
A first barrier layer, preferably tetraethyl orthosilicate (TEOS), is disposed over the semiconductor substrate, the thick field oxide areas, the source region, the drain region, and the transistor gate member. A second barrier layer (preferably made of borophosphosilicate glass (BPSG), borosilicate glass (BSG), phosphosilicate glass (PSG), or the like) is deposited over the first barrier layer. It is, of course, understood that a single barrier layer could be employed. However, a typical barrier configuration is a layer of TEOS over the transistor gate member and the substrate followed by a BPSG layer over the TEOS layer. The TEOS layer is applied to prevent dopant migration. The BPSG layer contains boron and phosphorus which can migrate into the source and drain regions formed on the substrate during inherent device fabrication heating steps. This migration of boron and phosphorus can change the dopant concentrations in the source and drain regions, which can adversely affect the performance of the transistor gate member.
The second barrier layer is then planarized down to the transistor gate member. The planarization is preferably performed using a mechanical abrasion, such as a chemical mechanical planarization (CMP) process. A first etch mask is patterned on the surface of the planarized second barrier layer, such that openings in the first etch mask are located substantially over the source region and the drain region. The first etch mask openings may be of any shape or configuration, including, but not limited to, circles, ovals, rectangles, or even long slots extending over several source regions or drain regions, respectively. The second barrier layer and first barrier layer are then etched to form first vias which expose at least a portion of the source region and the drain region, and the first etch mask is removed. The exposure of the transistor gate member and the etching of such a shallow second barrier layer and first barrier layer allow for easy alignment of the first etch mask which, of course, virtually eliminates the possibility of etching through the insulating material of the transistor gate member to expose and short the gate conducting layer within the transistor gate member. A first conductive material is deposited to fill the first vias. The first conductive material is then planarized to isolate the first conductive material within the first vias, thereby forming contact plugs.
Although any shape of openings in the first etch mask can be used, such as individual openings for each source and drain region, it is preferred that a plurality of transistors are formed in parallel, such that long, slot-type openings in the first etch mask can be formed. The long, slot-type opening, upon etching, forms long, slot vias, which expose multiple source regions or multiple drain regions, respectively. Thus, when the first conductive material is deposited in the first vias, the first conductive material will span multiple source or drain regions and, thereby, dissipate an ESD more efficiently.
A deposition mask is patterned on the second barrier layer, having openings over the contact plugs. The deposition mask openings may be of any shape or configuration, including, but not limited to, circles, ovals, rectangles, or even long slots extending over several source regions and drain regions, respectively. A second conductive material is deposited over the deposition mask to fill the deposition mask openings. The second conductive material is planarized to electrically separate the second conductive material within each deposition mask opening. The planarization is preferably performed using a mechanical abrasion, such as a CMP process. The deposition mask is then removed to leave the second conductive material forming contact lands which are preferably wider than the contact plugs. Again, it is preferred that the contact lands extend over multiple source or drain regions to assist in the dissipation of an ESD.
A third barrier layer (preferably made of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), or the like) is deposited over the second barrier layer and the contact lands, and, optionally, planarized. A second etch mask is patterned on the third barrier layer, wherein the second etch mask includes openings substantially aligned over the contact lands. The third barrier layer is then etched down to the contact lands to form contact vias. As mentioned above, the contact lands are preferably larger than the contact plugs. The larger contact lands provide a bigger xe2x80x9ctargetxe2x80x9d for the etch through the third barrier layer to xe2x80x9chitxe2x80x9d the contact lands in the formation of the contact vias. Thus, precise alignment becomes less critical.
The second etch mask is then removed and a third conductive material is deposited over the third barrier layer to fill the contact vias. The third conductive material is then planarized down to the third barrier layer, such as by a CMP method, to electrically isolate the conductive material within each contact via to form upper contacts. A second deposition mask is patterned on the third barrier layer, having openings over the upper contacts. A fourth conductive material is deposited over the deposition mask to fill the deposition mask openings. The fourth conductive material is planarized to electrically separate the fourth conductive material within each deposition mask opening. The planarization is preferably performed using a mechanical abrasion, such as a CMP process. The second deposition mask is then removed to leave the fourth conductive material, forming a source contact metallization and a drain contact metallization, thereby completing the formation of the transistor.